The present invention is directed to thermoelectric structure and method of making the same. More particularly, the invention provides a method for the manufacture of nanostructured thermoelectric elements. Merely by way of an example, the method has been applied to uniwafer backend processing for forming a plurality of thermoelectric legs based on nanowires in a single silicon wafer. It would be recognized that the invention has a much broader range of applicability.
To date, thermoelectrics have had limited commercial applicability due to the poor cost performance of these devices compared to other technologies that accomplish similar means of energy generation or refrigeration. Where other technologies usually are not as suitable as thermoelectrics for using in lightweight and low footprint applications, thermoelectric devices often have nonetheless been limited by their prohibitively high costs. Important in realizing the usefulness of thermoelectrics in commercial applications is the manufacturability of devices that comprise high-performance thermoelectric materials (e.g., modules). These modules are preferably produced in such a way that ensures, for example, maximum performance at minimum cost.
The thermoelectric materials in presently available commercial thermoelectric modules are generally comprised of bismuth telluride or lead telluride, which are both toxic, difficult to manufacture with, and expensive to procure and process. With a strong present need for both alternative energy production and microscale cooling capabilities, the driving force for highly manufacturable, low cost, high performance thermoelectrics is growing.
Thermoelectric devices are often divided into thermoelectric legs made by conventional thermoelectric materials such as Bi2Te3 and PbTe, contacted electrically, and assembled in a refrigeration (e.g., Peltier) or energy conversion (e.g., Seebeck) device. This often involves bonding the thermoelectric legs to metal contacts in a configuration that allows a series-configured electrical connection while providing a thermally parallel configuration, so as to establish a temperature gradient across all the legs simultaneously. However, many drawbacks may exist in the production of conventional thermoelectric devices. For example, costs associated with processing and assembling the thermoelectric legs made externally is often high. The conventional processing or assembling method usually makes it difficult to manufacture compact thermoelectric devices needed for many thermoelectric applications. Conventional thermoelectric materials are usually toxic and expensive.
Nanostructures often refer to structures that have at least one structural dimension measured on the nanoscale (e.g., between 0.1 nm and 1000 nm). For example, a nanowire is characterized as having a cross-sectional area that has a distance across that is measured on the nanoscale, even though the nanowire may be considerably longer in length. In another example, a nanotube, or hollow nanowire, is characterized by having a wall thickness and total cross-sectional area that has a distance across that is measured on the nanometer scale, even though the nanotube may be considerably longer in length. In yet another example, a nanohole is characterized as a void having a cross-sectional area that has a distance across that is measured on the nanoscale, even though the nanohole may be considerably longer in depth. In yet another example, a nanomesh is an array, sometimes interlinked, including a plurality of other nanostructures such as nanowires, nanotubes, and/or nanoholes.
Nanostructures have shown promise for improving thermoelectric performance. The creation of 0D, 1D, or 2D nanostructures from a thermoelectric material may improve the thermoelectric power generation or cooling efficiency of that material in some instances, and sometimes very significantly (a factor of 100 or greater) in other instances. However, many limitations exist in terms of alignment, scale, and mechanical strength for the nanostructures. Processing such nanostructures using methods that are similar to the processing of silicon would have tremendous cost advantages. For example, creating nanostructure arrays in a wafer with long uniform lengths ending with planar frontend surfaces can be utilized in planar semiconductor processes. The processes may include etching the bulk-like wafer to from arrays of nanowires, filling a matrix material to embed the arrays of nanowires, and performing end-region metallization of the nanowires, and more. Eventually, processing the nanostructure arrays in these planar processes is aimed to cause a formation of a plurality of nanostructured thermoelectric legs configured for assembling an actual macroscopic thermoelectric device with greatly improved thermoelectric performance.
Nanostructure arrays, including nanowires, nanotubes, nanoholes, or a mesh network of above nanostructures, can be fabricated directly out of a silicon wafer material. For example, arrays of nanowires are formed substantially vertically into a thickness of the silicon wafer up to 400 microns or greater. More details about formation of arrays of long nanostructures in semiconductor materials and methods thereof can be found in U.S. patent application Ser. No. 13/299,179 filed Nov. 17, 2011 commonly assigned to Alphabet Energy, Inc. Hayward, Calif., incorporated as references for all purposes. It is desirable to transform these special nanostructure arrays into high performance thermoelectric (TE) elements by utilizing the high electrical conductance and low thermal conductance functionalities of the long nanowires to give a high thermoelectric figure of merit ZT value. The ultimate commercial performance, and therefore usefulness, of a power generation thermoelectric is governed by its cost-per-Watt. It is beneficial to process a single piece of material, for example, a silicon wafer, in such a fashion as its use as a thermoelectric is maximized, since processing steps for most two-dimensional semiconductor material or the like cost the same amount regardless of the material thickness.
Particularly in an embodiment, the arrays of SiNW can be doped either in n or p-type with a doping level up to 1020 CM−3 to push up the electrical conductivity and its thermal conductivity is substantially reduced or limited by the extreme small cross section area for these nanowires with aspect ratio of about 100 to 1, or even 1000:1. In another embodiment, the arrays of SiNW on silicon wafer, a so-called SiNWs on uniwafer structure, are embedded into a dielectric fill material that bears a high dielectric constant and substantially low thermal conductivity. More details on methods for embedding Si nanowire arrays into a matrix of fill material for forming thermoelectric elements can be found in U.S. patent application Ser. No. 13/308,945 filed Dec. 1, 2011, commonly assigned to Alphabet Energy, Inc. of Hayward, Calif., incorporated as references for all purposes. However, provided with a thermoelectric uniwafer structure with the arrays of SiNW embedded in a matrix of fill material in a silicon wafer, further processes on transferring the SiNWs on uniwafer structures to useful bulk-sized thermoelectric legs for the manufacture of thermoelectric devices are still scarce and desired.
From the above, it is seen that improved techniques for manufacturing thermoelectric device based on SiNWs on uniwafers are desired.